Conventionally, as a nonvolatile memory capable of storing two bits by one field-effect transistor, there has been a memory developed by Saifun Semiconductors Ltd. (refer to Kohyo (Japanese Unexamined Patent Publication) No. 2001-512290 for example). The structure of this prior art memory and the principle of its erase operation will be described hereinbelow.
As shown in FIG. 22 of the present application, this memory is composed of a gate electrode 909 formed on a P type well region 901 through a gate insulating film, and a first N type diffusion layer region 902 and a second N type diffusion layer region 903 formed on the surface of the P type well region 901. The gate insulating film is composed of so-called ONO (Oxide Nitride Oxide) film in which a silicon nitride film 906 is interposed between silicon oxide films 904 and 905. In the silicon nitride film 906, there are formed memory holing portions 907, 908 in the vicinity of the edge portions of the first and second N type diffusion layer regions 902, 903.
An amount of electric charges in each of these memory holing portions 907, 908 is read as a drain current of a transistor so that two-bit information is stored in one transistor.
Next description will be given of an erase operation method in this memory. The term “erase” is used herein to refer to the action of releasing electrons stored in the memory holing portions 907, 908. In Kohyo (Japanese Unexamined Patent Publication) No. 2001-512290, there has been disclosed a method for releasing electrons stored in a right memory holding portion 908 by applying 5.5V to the second diffusion layer region 903 and −8V to the gate electrode 909, and extracting electrons toward the drain electrode. This makes it possible to erase memory of a specific side among two memory holding portions. There has been also disclosed a method for writing onto and reading from a specific side. By combining these methods, two-bit operation is enabled.
However, in the above-stated memory, in order to provide the gate insulating film with the function of operating the transistor as well as the function as a memory film for storing electric charges, the gate insulating film is formed into three-layer structure with use of ONO film. This makes it difficult to manufacture thinner gate insulating films. Also, as the channel length is shortened, these two memory holing portions 907, 908 in one transistor interfere with each other, which makes two-bit operation difficult. This obstacles further miniaturization of the devices.